View FQD60N03L_303420.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FQD60N03L
April 2004
FQD60N03L
N-Channel Logic Level MOSFETs 30V, 30A, 0.023
General Description
This device employs advanced MOSFET technology and features low gate charge while maintaining low onresistance. Optimized for switching applications, this device improves the overall efficiency of DC/DC converters and allows operation to higher switching frequencies.
Features
* Fast switching * r DS(ON) = 0.014 (Typ), V GS = 10V * r DS(ON) = 0.024 (Typ), V GS = 4.5V * Qg (Typ) = 9.6nC, V GS = 5V * Qgd (Typ) = 3.4nC * C ISS (Typ) = 900pF
Applications
* DC/DC converters
DRAIN (FLANGE) GATE G SOURCE
D
TO-252AA
FDD SERIES
S
MOSFET Maximum Ratings T C=25C unless otherwise noted
Symbol V DSS V GS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (T C = 25 o C, V GS = 10V) ID Continuous (T C = 100 o C, V GS = 4.5V) Continuous (T C = 25 o C, V GS = 10V, R JA = 52 o C/W) Pulsed PD TJ, T STG Power dissipation Derate above 25 o C Operating and Storage Temperature 30 19 7.9 Figure 4 45 0.37 -55 to 150 A A A A W W/ o C
oC
Ratings 30 20
Units V V
Thermal Characteristics
R JC R JA R JA Thermal Resistance Junction to Case TO-252 Thermal Resistance Junction to Ambient TO-252 Thermal Resistance Junction to Ambient TO-252, 1in 2 copper pad area 2.73 100 52
o
C/W
o C/W o C/W
Package Marking and Ordering Information
Device Marking FQD60N03L Device FQD60N03L Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
FQD60N03L
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
B VDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V V DS = 25V V GS = 0V V GS = 20V TC = 125 oC 30 1 250 100 V A nA
On Characteristics
V GS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance V GS = VDS , ID = 250A ID = 30A, V GS = 10V ID = 19A, V GS = 4.5V 1 0.014 0.024 3 0.023 0.030 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(5) Qg(TH) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge (V GS = 4.5V) V DD = 15V, I D = 7.9A V GS = 4. 5V, RGS = 18 (V GS = 10V) V DD = 15V, I D = 7.9A V GS = 10 V, RGS = 18 6 26 52 28 48 120 ns ns ns ns ns ns 11 49 27 28 90 83 ns ns ns ns ns ns V DS = 15V, V GS = 0V, f = 1MHz V GS = 0V to 10V V GS = 0V to 5V V DD = 15V V GS = 0V to 1V ID = 19A Ig = 1.0mA 900 210 90 18 9.6 1.0 3.4 3.4 28 14 1.5 pF pF pF nC nC nC nC nC
Switching Characteristics
tO N td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Switching Characteristics
tO N td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Unclamped Inductive Switching
tAV Avalanche Time ID = 2.7 A, 3.0 mH 180 s
Drain-Source Diode Characteristics
V SD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 19A ISD = 10A ISD = 19A, dI SD /dt = 100A/s ISD = 19A, dI SD /dt = 100A/s 1.25 1.0 58 70 V V ns nC
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
FQD60N03L
Typical Characteristic
1.2 40
POWER DISSIPATION MULTIPLIER
1.0 ID , DRAIN CURRENT (A) 30 VGS = 10V
0.8
0.6
20 V GS = 4.5V 10
0.4
0.2
0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE ( o C)
0 25 50 75 100 125 150 TC , CASE TEMPERATURE (o C)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
Z JC , NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1 /t 2 PEAK TJ = P DM x Z JC x RJC + TC 10 -3 10 -2 t, RECTANGULAR PULSE DURATION (s) 10-1 10 0 101
0.01 10 -5
10-4
Figure 3. Normalized Maximum Transient Thermal Impedance
500 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION I DM, PEAK CURRENT (A) VGS = 10V TC = 25o C FOR TEMPERATURES ABOVE 25 o C DERATE PEAK CURRENT AS FOLLOWS: I = I25 100 V GS = 5V 150 - TC 125
20 10 -5 10-4 10 - 3 10 - 2 t, PULSE WIDTH (s) 10 -1 10 0 101
Figure 4. Peak Current Capability
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
FQD60N03L
Typical Characteristic (Continued)
60 TJ = 25 C I D , DRAIN CURRENT (A) ID , DRAIN CURRENT (A)
o
60 V GS = 10V V GS = 4.5V
40
40 VGS = 3.5V
20 TJ = 150 o C TJ = -55 o C 0 1 2 3 4 5
20
V GS = 3.0V PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX TC = 25o C
0 0 VGS , GATE TO SOURCE VOLTAGE (V) 0.5 1.0 1.5 2.0 V D S, DRAIN TO SOURCE VOLTAGE (V) 2.5
Figure 5. Transfer Characteristics
50 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX rD S(ON ), DRAIN TO SOURCE ON RESISTANCE (m) 40 ID = 30A 30 ID = 7.9A
Figure 6. Saturation Characteristics
2.0 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX
1.5
1.0
20
VGS = 10V, ID = 30A 10 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE ( o C)
Figure 7. Drain to Source On Resistance vs Gate Voltage and Drain Current
1.4
Figure 8. Normalized Drain to Source On Resistance vs Junction Temperature
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
VGS = VDS , I D = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.2
ID = 250A
1.1
1.0
0.8
1.0
0.6
0.4 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (o C)
0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE ( o C)
Figure 9. Normalized Gate Threshold Voltage vs Junction Temperature
Figure 10. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
FQD60N03L
Typical Characteristic (Continued)
2000 1000 C, CAPACITANCE (pF) V GS, GATE TO SOURCE VOLTAGE (V) CISS = C GS + C GD 10 V DD = 15V 8
COSS CGS + CGD
6
CRSS = CGD
4 WAVEFORMS IN DESCENDING ORDER: ID = 30A ID = 15A 0 3 6 9 Q g , GATE CHARGE (nC) 12 15
2
100 70 0.1
V G S = 0V, f = 1MHz 1 10 30
0 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Capacitance vs Drain to Source Voltage
100 VGS = 4.5V, V D D = 15V, ID = 7.9A tr 80 SWITCHING TIME (ns)
Figure 12. Gate Charge Waveforms for Constant Gate Currents
140 VGS = 10V, VD D = 15V, ID = 7.9A 120 SWITCHING TIME (ns)
tf 60 t d(OFF) 40
td(OFF) 100 80 60 40 tr 20 0 td(ON)
tf
20
td(ON)
0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50
0
10 20 30 40 RGS, GATE TO SOURCE RESISTANCE ( )
50
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS tP L IAS VARY t P TO OBTAIN REQUIRED PEAK I AS VGS DUT tP 0V RG -
BVDSS
VD S VD D
+
VDD
IAS 0.01
0 tA V
Figure 15. Unclamped Energy Test Circuit
(c)2004 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
FQD60N03L Rev. B1
FQD60N03L
Test Circuits and Waveforms (Continued)
VD S RL
VDD VDS
Q g(TOT)
VGS = 10V VGS Qg(5) VD D DUT I g(REF) 0 V GS VGS = 1V Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
+
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VD S
t ON t d(ON) RL VDS 90% tr
t OFF td(OFF) tf 90%
+
VGS DUT RGS
VDD 0
10%
10%
90% V GS 50% PULSE WIDTH 50%
V GS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
FQD60N03L
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T M, and the J thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P DM, in an application. Therefore the application's ambient temperature, T A (o C), and thermal resistance R JA ( o C/W) must be reviewed to ensure that T JM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P D M = ----------------------------R JA
125 RJA = 33.32+ 23.84/(0.268+Area) EQ.2 100 R JA ( o C/W) R JA = 33.32+ 154/(1.73+Area) EQ.3
75
(EQ. 1)
50
In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the R JA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeter square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA =
25 0.01 (0.0645)
0.1 (0.645)
1 (6.45)
10 (64.5)
AREA, TOP COPPER AREA in2 (cm2 )
Figure 21. Thermal Resistance vs Mounting Pad Area
23.84 33.32 + ------------------------------------( 0.268 + Area ) 154 33.32 + ---------------------------------( 1.73 + Area)
(EQ. 2)
Area in Inches Squared
R JA =
(EQ. 3)
Area in Centimeters Squared
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
FQD60N03L
PSPICE Electrical Model
.SUBCKT FQD60N03L 2 1 3 ; CA 12 8 5.0e-10 CB 15 14 3.9e-10 CIN 6 8 7.8e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 31.0 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
LGATE
rev June 02
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 EBREAK RLDRAIN DBREAK 11 + 17 18 5 DRAIN 2
RSLC2
5 51 ESG + GATE 1 RLGATE EVTEMP RGATE + 18 9 20 22 6 8 -
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 4.53e-9 LSOURCE 3 7 5.38e-10
MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.2e-3 RGATE 9 20 2.8 RLDRAIN 2 5 10 RLGATE 1 9 45.3 RLSOURCE 3 7 5.4 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.0e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),3.5))} .MODEL M=0.62) .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .MODEL .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. DBODYMOD D (IS = 3.5e-11 N=1.12 RS = 6.4e-3 TRS1 = 1e-3 TRS2 = 2.0e-6 XTI=2.3 C J O = 6 . 1 e - 1 0 T T = 1 e - 8 DBREAKMOD D (RS = 6.0e-1 TRS1 = 1e-3 TRS2 = -8.5e-6) DPLCAPMOD D (CJO = 3.4e-10 IS = 1e-30 N = 10 M = 0.45) MMEDMOD NMOS (VTO = 1.68 KP = 3.5 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.8) MSTROMOD NMOS (VTO = 2.00 KP = 35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28 RS = 0.1) RBREAKMOD RES (TC1 = 1e-3 T C 2 = - 1 e - 7 ) RDRAINMOD RES (TC1 = 3.4e-2 TC2 = 6.0e-5) RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -8e-6) RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1e-6) S1AMOD S1BMOD S2AMOD S2BMOD VSWITCH VSWITCH VSWITCH VSWITCH (RON (RON (RON (RON = = = = 1e-5 1e-5 1e-5 1e-5 ROFF ROFF ROFF ROFF = = = = 0.1 V O N 0.1 V O N 0.1 V O N 0.1 V O N = = = = - 4 . 0 VOFF= -1.5) - 1 . 5 VOFF= -4.0) - 0 . 5 VOFF= 0.3) 0.3VOFF= -0.5)
(c)2004 Fairchild Semiconductor Corporation
+
DBODY
MWEAK MMED
FQD60N03L Rev. B1
FQD60N03L
SABER Electrical Model
REV June 2002 template FQD60N03L n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 3.5e-11, nl=1.12, rs = 6.4e-3, trs1 = 1e-3, trs2 = 2e-6, xti=2.3, cjo = 6.1e-10, tt = 1e-8, m = 0.6 2) dp..model dbreakmod = (rs = 6e-1, trs1 = 1e-3, trs2 = -8.5e-6) dp..model dplcapmod = (cjo = 3.4e-10, isl=10e-30, nl=10, m=0.45) m..model mmedmod = (type=_n, vto = 1.68, kp=3.5, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.00, kp = 35, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.36, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3) LDRAIN sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5) DPLCAP 5 DRAIN c.ca n12 n8 = 5.0e-10 c.cb n15 n14 = 3.9e-10 c.cin n6 n8 = 7.8e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
ESG 10 RSLC1 51 RSLC2 ISCL 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 9 20 22 6 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED MSTRO 8 EBREAK + 17 18 DBREAK 11 RLDRAIN 2
i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 4.53e-9 l.lsource n3 n7 = 5.38e-10
DBODY
LSOURCE 7 RLSOURCE 18 RVTEMP
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -1e-7 res.rdrain n50 n16 = 1.2e-3, tc1 = 3.4e-2, tc2 = 6e-5 res.rgate n9 n20 = 2.8 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 45.3 res.rlsource n3 n7 = 5.4 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1e-2, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -8e-6 spe.ebreak n11 n7 n17 n18 = 31.0 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a sw_vcsp.s1b sw_vcsp.s2a sw_vcsp.s2b n6 n12 n13 n8 = model=s1amod n13 n12 n13 n8 = model=s1bmod n6 n15 n14 n13 = model=s2amod n13 n15 n14 n13 = model=s2bmod
12 S1A 13 8 13 + EGS 6 8 S2A 14 13 S2B CB + EDS 5 8 14 15
SOURCE 3
RSOURCE RBREAK 17
S1B CA
IT
19 VBAT + 22 RVTHRES
8
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/120))** 3.5)) } }
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
FQD60N03L
SPICE Thermal Model
REV June 2002 FQD60N03LT CTHERM1 th 6 1.3e-3 CTHERM2 6 5 1.5e-3 CTHERM3 5 4 1.6e-3 CTHERM4 4 3 1.7e-3 CTHERM5 3 2 5.8e-3 CTHERM6 2 tl 4.0e-2 RTHERM1 th 6 2.7e-3 RTHERM2 6 5 3.7e-3 RTHERM3 5 4 5.3e-2 RTHERM4 4 3 6.3e-1 RTHERM5 3 2 7.4e-1 RTHERM6 2 tl 7.6e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FQD60N03LT template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.3e-3 ctherm.ctherm2 6 5 = 1.5e-3 ctherm.ctherm3 5 4 = 1.6e-3 ctherm.ctherm4 4 3 = 1.7e-3 ctherm.ctherm5 3 2 = 5.8e-3 ctherm.ctherm6 2 tl = 4.0e-2 rtherm.rtherm1 th 6 = 2.7e-3 rtherm.rtherm2 6 5 = 3.7e-3 rtherm.rtherm3 5 4 = 5.3e-2 rtherm.rtherm4 4 3 = 6.3e-1 rtherm.rtherm5 3 2 = 7.4e-1 rtherm.rtherm6 2 tl = 7.6e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2004 Fairchild Semiconductor Corporation
FQD60N03L Rev. B1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM FACT Quiet SeriesTM ActiveArrayTM FAST BottomlessTM FASTrTM CoolFETTM FPSTM CROSSVOLTTM FRFETTM DOMETM GlobalOptoisolatorTM EcoSPARKTM GTOTM E2CMOSTM HiSeCTM EnSignaTM I2CTM FACTTM i-LoTM Across the board. Around the world.TM The Power Franchise Programmable Active DroopTM
DISCLAIMER
ImpliedDisconnectTM PACMANTM POPTM ISOPLANARTM Power247TM LittleFETTM MICROCOUPLERTM PowerSaverTM PowerTrench MicroFETTM QFET MicroPakTM QSTM MICROWIRETM QT OptoelectronicsTM MSXTM Quiet SeriesTM MSXProTM RapidConfigureTM OCXTM RapidConnectTM OCXProTM SILENT SWITCHER OPTOLOGIC SMART STARTTM OPTOPLANARTM
SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I10

▲Up To Search▲

Price & Availability of FQD60N03L

	To Download FQD60N03L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .